The invention relates to tracking signals.
Memory cells in memory devices, such as dynamic random access memories (DRAMs), are typically arranged in arrays. Portions of an exemplary array 14 in a memory device 8 are shown in FIG. 1. A memory cell, such as cell 18, is selected for access by activation of a wordline signal WLi driven by a row address decoder 10 and activation of a column select signal YSi driven by a column address decoder 12. Each memory cell is connected to one of a pair of bit lines BL and BL.sub.-- through a pass transistor, such as n-channel MOSFET 16. The bit lines are connected to sense amplifiers 20, which when activated drive BL and BL.sub.-- to opposite states depending on the charge stored in the connected memory cell.
Upon completion of an access to the array 14, the sense amplifiers 20 are shut off. To ensure that each bit line pair EL/BL.sub.-- is precharged to a known state, a signal decoder 22 drives a precharge activation signal P1 to the sense amplifiers 20 to equalize the bit lines BL and BL.sub.--, typically to half an internal power supply voltage Vccr. Thus, when the array 14 is inactive, the bit lines are maintained at the equalization voltage (Veq).
When a wordline signal WLi is driven high (typically to an elevated voltage Vccp that is greater than the internal power supply voltage Vccr, as shown in FIG. 2), all the pass transistors connected to the wordline signal are activated. As a result, the charges stored in the selected memory cells flow onto corresponding bit lines BL or BL.sub.--. In the timing diagram shown in FIG. 2, the cell 18 is assumed to contain a "0" charge, which causes the bit line BL to be pulled lower than the complementary bit line BL.sub.--. If the cell 18 contains a "1", then the bit line BL would be pulled to a slightly higher voltage then BL.sub.--.
After the wordline signal WLi is turned on, the sense amplifiers 20 are activated by a strobe signal S1 driven by the signal decoder 22. At some later time, the column decoder 12 asserts one of the column select signals YSi to output the selected bit onto input/output lines IOi and IOi.sub.-- connected to the outputs of the sense amplifiers 20.
Referring to FIG. 3, a tracking circuit 24 is shown that has been used in some DRAM devices to track the wordline signals to control the strobe signal S1 and precharge activation signal P1. An RC network 100 models the resistance and capacitance of a wordline signal WLi, the RC network providing a signal MWL that is driven by a model wordline driver 23 from row control signals. The capacitance of the network 100 is obtained by connecting an n-channel MOSFET 101 having the equivalent width of the multiple n-channel MOSFETs connected to a wordline WLi in the array 14.
The tracking circuit 24 includes a low trip point detector 130 having p-channel MOSFETs 102 and 104 and n-channel MOSFETs 106 and 108 connected in series between Vccr and Vss, as well as a high trip point detector 132 having p-channel MOSFETs 110 and 112 and n-channel MOSFETs 114 and 116, also connected in series between Vccr and Vss. The model wordline signal MWL is connected to the gate of each of the MOSFETs 104, 106, 112 and 114. The sources of p-channel MOSFETs 104 and 112 and the drains of n-channel MOSFETs 106 and 114 are connected to a common node N1, which is further connected to the input of an inverter 118. The output of the inverter 118 is connected to the gates of p-channel MOSFET 110 and n-channel MOSFET 108, as well as to the input of an inverter 120. The output of the inverter 120 is connected to the gates of n-channel MOSFET 116 and p-channel MOSFET 102, as well as to an inverter 122, which outputs a signal WLTRACK used by the signal decoder 22 to control S1 and P1.
The transistors 110, 112, 114, and 116 are sized to provide a relatively high trip point; that is, the output driven by the MOSFETs 110, 112, 114, and 116 does not transition low in response to the model wordline signal MWL transitioning high until it reaches a predetermined high voltage. The transistors 102, 104, 106, and 108 are sized to provide a low trip point; that is, the output driven by the MOSFETs 102, 104, 106, and 108 does not transition high in response to the signal MWL transitioning low until it has reached a predetermined low voltage. In this manner, the signal WLTRACK is not asserted or deasserted until the signal MWL has transitioned to predetermined voltage levels.